AN1087/0998 1/8 application note st9+ interrupt response time by microcontroller division applications 1 introduction this application note presents the st9+ interrupt response time calculation for each kind of in- terrupt in the best and the worst cases. the interrupt response time is the time between the in- terrupt event occurrence and the start of the corresponding interrupt service routine. the different phases of interrupt processing are described in section 2. the arbitration phase takes place in parallel with the program flow. during this phase, the in- terrupt request with the highest priority is selected in order to be serviced if its priority is higher than the current priority level (cpl). the second phase is to wait for the end of the current non-interruptable sequence in process. the last phase is the exception handling, that is to say the time required to service the inter- rupt. 2 interrupt processing phases 2.1 arbitration phase the interrupt arbitration protocol functions continuously and completely asynchronously from instruction flow. it analyzes the different request priorities and selects the interrupt which will be serviced next. an arbitration lasts 5 clock cycles and is composed of 5 phases (1 ck per phase): phase a (ck1): start of arbitration phase b (ck2): prl<2> of cpu/peripherals arbitration phase c (ck3): prl<1> of cpu/peripherals arbitration phase d (ck4): prl<0> of cpu/peripherals arbitration phase e (ck5): interrupt request information arbitration prl means `priority level bit x'. the various (software programmable) priority levels of the peripherals and cpu are arbitrated first, and then the pending interrupt requests. if an interrupt (or dma) request is pending, it is acknowledged during a sixth phase: phase f (ck6): interrupt acknowledge 1
st9+ interrupt response time 2/8 2.2 non-interruptable sequence timing analysis in the st9+ microcontroller, an instruction can be interrupted if the register file and the memory have not yet been modified by this instruction. this feature reduces the interrupt re- sponse time. however, each instruction contains a non-interruptable sequence which must be completed before the pending interrupt can be serviced. the longest non-interruptable sequence is located inside the div instruction and lasts 22 clock cycles. for the divws and mul instructions, it lasts 20 clock cycles. for other instruc- tions, it can be considered 16 clock cycles long. for further calculations the worst case can be taken into account, that is to say, 22 clock cy- cles. however, in most cases this phase is only 16 clock cycles long. on the other hand, the shortest non-interruptable sequence is the last clock cycle of an in- struction (1 clock cycle long). 2.3 exception handling phase the exception handling phase performs the following steps: disables all maskable interrupt requests by clearing the ien bit in the cicr register. pushes the 16-bit pc (program counter) onto the system stack. pushes the flagr register onto the system stack. loads the pc with the 16-bit vector stored in the vector table, pointed to by the interrupt vector register (ivr). this phase lasts 18 clock cycles when the system stack is located in memory if the system stack is located in the register file, 2 more clock cycles are needed. instructions operating on the register file are normally faster than those operating on the memory. this is due to the fact that the register file access is overlapped with instruction fetches. but in the case of interrupts, it is not possible to fetch anything before all pushes are completed, so the stack in the register file is not a faster option. moreover, when the stack is in the memory, you can benefit from the bus parallelism between the data register bus (drb) and the multiplexed memory bus (mmb). this is why, during exception handling, using the system stack in the register file is 2 clock cycles longer than using the system stack in memory. if you need to access more than 64k bytes of interrupt routine code, you have to save the csr register in the stack during exception handling, together with the pc and the flag register. this is done by setting the encsr bit in the emr2 register. with this option, 2 additional clock cycles are needed to complete the interrupt cycle, as the csr is pushed onto the system stack.
3/8 st9+ interrupt response time depending on the options you have chosen in your application, you will have different results for your interrupt response duration. this is summarized in the following table. table 1. exception handling duration 3 interrupt response time calculations from the information described in the section 2, the best and worst case interrupt response times have been calculated for the various existing sources of st9+ interrupts: internal interrupts external interrupts nmi pin top level interrupt watchdog timer top level interrupt for the times listed below, the phases during which the described event takes place are shown in brackets. these phases are described in the section 2.1 (arbitration phase). 3.1 internal interrupts internal interrupts are interrupts generated by the st9+ on-chip peripherals. for example, the multifunction timer `end of count' interrupt, or the serial peripheral interface `end of byte transmission' interrupt. n best case valid arbitration + acknowledge (pha,phb,phc,phd,phe,phf): 6ck shortest non-interruptable sequence: 1ck exception handling duration (best case): 18ck total 25ck n worst case missed arbitration (phb,phc,phd,phe): 4ck valid arbitration + acknowledge (pha,phb,phc,phd,phe,phf): 6ck longest non interruptable sequence: 22ck exception handling duration (worst case): 22ck total 54ck encsr system stack exception handling duration 0 memory 18 clock cycles 1 memory 20 clock cycles 0 register file 20 clock cycles 1 register file 22 clock cycles
st9+ interrupt response time 4/8 as an arbitration (without acknowledge) is 5 clock cycles long, the arbitration is missed if the interrupt occurs just after the beginning of the arbitration phase (during phb): so, a missed ar- bitration is 4 clock cycles long. refer to figure 1 for an illustation of the worst case response time with the various phases used in the calculation. figure 1. internal interrupts maximum response time 3.2 external interrupts external interrupts are interrupts coming from the external st9+ interrupt pins. for example, a falling edge on the int2 pin. note: interrupts coming from st9+ on-chip peripherals but sharing an external interrupt channel are not external interrupts: they are internal interrupts. please refer to the previous paragraph for the internal interrupts response time calculations. n best case external interrupt sampling (phe): 1ck valid arbitration + acknowledge (pha,phb,phc,phd,phe,phf): 6ck shortest non-interruptable sequence: 1ck exception handling duration (best case): 18ck total 26ck n worst case external interrupt sampling (pha): 1ck missed arbitration (phb,phc,phd,phe): 4ck valid arbitration + acknowledge (pha,phb,phc,phd,phe,phf): 6ck longest non interruptable sequence: 22ck exception handling duration (worst case): 22ck interrupt exc. handling response time 54 intclk cycles max missed arbitration valid arbitration (in st9+ instructioncan be interruptedif they haven't modified yet registers or memory) instruction n+1 instruction n non interrupt. sequence. 5-1=4 intclk 6intclk 22 22 5intclk (+acknowledge) in the st9+, inst ructions can be modifie d if they haven't yet modifi ed registe rs or memory
5/8 st9+ interrupt response time total 55ck 3.3 nmi pin top level interrupt the nmi pin top level interrupt is the interrupt generated by a rising or a falling edge (de- pending on the chosen configuration) on the nmi pin of the st9+. the nmi interrupt is a top level interrupt the nmi source is selected when the tlis bit of the eivr register is reset (=default value). n best case external nmi interrupt sampling (phd): 1ck valid arbitration + acknowledge (phe,phf): 2ck shortest non interruptable sequence: 1ck exception handling duration (best case): 18ck total 22ck as the nmi is a top level interrupt, it overrides every other priority. it is why pha, phb, phc, and phd of the arbitration are not required in the top level interrupt arbitration: a top level interrupt sampled during phd is thus taken into account (best case above). as shown below, the worst case is when the nmi interrupt is sampled during the next phase (phe), so that all the arbitration phases must be completed in this case (even if they are not useful for the top level interrupt). n worst case external nmi interrupt sampling (phe): 1ck valid arbitration + acknowledge (pha,phb,phc,phd,phe,phf): 6ck longest non interruptable sequence: 22ck exception handling duration (worst case): 22ck total 51ck
st9+ interrupt response time 6/8 3.4 watchdog timer top level interrupt the watchdog timer `end of count' (eoc) interrupt is generated when the watchdog timer counter reaches 0 (if the watchdog timer is used as a normal timer, not in watchdog mode). this eoc interrupt can be configured to be the source of the inta0 interrupt channel or the source of the top level interrupt channel. the watchdog timer interrupt configured to share the interrupt channel of int0 pin is an in- ternal interrupt (see 3.1 for corresponding calculation). the calculation below is relevant for the watchdog timer interrupt configured as a source of the top level interrupt request. n best case valid arbitration + acknowledge (phe,phf): 2ck shortest non-interruptable sequence: 1ck exception handling duration (best case): 18ck total 21ck n worst case valid arbitration + acknowledge (pha,phb,phc,phd,phe,phf): 6ck longest non-interruptable sequence: 22ck exception handling duration (worst case): 22ck total 50ck
7/8 st9+ interrupt response time 4 summary all the results of the different cases studied before are summarized in the following table. moreover is calculated the time corresponding to the calculated clock cycles, with a st9+ in- ternal frequency of 24 mhz. table 2. interrupt response time summary thanks to these values, you can calculate the duration of any of your interrupts, by adding the corresponding interrupt response time value found in the table above to your interrupt code time, plus the length of the iret instruction (12, 14, or 16 clock cycles, depending on the value of the encsr bit in the emr2 register, and of the system stack location, in the same way as described in the exception handling duration calculation in the paragraph 2.3). kind of interrupt worst case best case clock cycles m s (at 24mhz) clock cycles m s (at 24mhz) internal interrupt 54 2.25 25 1.04 external interrupt 55 2.29 26 1.08 nmi top level interrupt 51 2.12 22 0.92 watchdog timer tli 50 2.08 21 0.87
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